1. Field
Embodiments described herein relate generally to a nonvolatile semiconductor memory device.
2. Description of the Related Art
Conventionally, as an electrically rewritable nonvolatile memory, a flash memory is known which includes a cell array configured by NAND connection or NOR connection of memory cells each having a floating gate structure. Further, a ferroelectric memory is also known as a memory that is nonvolatile and compatible with fast random access.
Meanwhile, as a technique for enabling greater miniaturization of memory cells, a resistance varying memory using a variable resistance element in each memory cell is proposed. Known variable resistance elements include: a phase change memory element varying a resistance by phase changes of a chalcogenide compound between a crystallized state and an amorphous state; an MRAM element using resistance changes due to tunnel magnetoresistance effect; a memory element of a polymer ferroelectric RAM (PFRAM) including a resistance element made of a conductive polymer; a ReRAM element inducing resistance changes upon electric pulse application, etc (Patent Document 1: JP 2006-344349A, paragraph 0021).
In the resistance varying memory, memory cells can be configured by a series circuit of not a transistor but a Schottky diode and a variable resistance element. Therefore, memory cells can be easily stacked to a three-dimensional structure and hence are advantageous for grater miniaturization (Patent Document 2: JP 2005-522045A).
However, a relatively large current flows through this resistance varying memory and its interconnection lines in a reset operation of changing the resistance state of the variable resistance element from a low resistance state to a high resistance state and in a read operation of sensing the resistance state of the variable resistance element. Therefore, influence of a voltage drop due to an interconnection resistance is unignorable. That is, since the influence of a voltage drop varies depending on the location to be accessed, a read margin and a reset margin are reduced. Furthermore, there is also a problem that the number of bits that can be accessed simultaneously is limited.